1. Field of the Invention
The present invention relates generally to digital demodulators, and more particularly, to a digital demodulator used as a MODEM for digital communication equipment such as a land mobile radio telephone, a portable radio telephone and a cordless telephone.
2. Description of the Background Art
A conventional digital communication apparatus modulates a carrier signal in response to a digital information signal (baseband signal) on the transmitting side, and demodulates the modulated signal on the receiving side to extract the information signal in order to achieve efficient transmission.
Such modulation systems include: an amplitude shift keying (ASK) system in which an amplitude of a carrier is changed in response to a digital baseband signal, a frequency shift keying (FSK) system in which a frequency of a carrier is deviated in response to a baseband signal, a phase shift keying (PSK) system in which a phase of a carrier is changed in response to a baseband signal, and a quadrature amplitude modulating (QAM) system in which an amplitude and a phase of a carrier are individually changed in response to a baseband signal.
The carrier signal (hereinafter referred to as "modulated signal") S(t) thus modulated in response to a baseband signal can be generally expressed by the following equation. ##EQU1##
In the above equation, A(t) denotes an amplitude, .omega..sub.c denotes a carrier frequency, and .PHI.(t) denotes a phase of a baseband signal.
As is clear from the above-described equation (1), the modulated signal can be represented by two components orthogonal to each other, that is, by a sum of an in-phase (I phase) component (the first term of the above-described equation (1)) and a quadrature phase (Q phase) component (the second term of the above-described equation (1)). Such a modulated signal can be therefore formed by using a quadrature modulator.
FIGS. 1 and 2 are a block diagram and a spatial diagram conceptually showing the principle of such a quadrature modulator, respectively. It should be noted that the following shows a phase modulating system for changing a phase of a carrier in response to a baseband signal, in which an amplitude A(t) is fixed to "1".
Referring to FIG. 1, a mapping circuit 2 provides I phase and Q phase components of a modulating wave signal as rectangular wave signals in response to a digital baseband signal applied through an input terminal 1. The I phase component is applied to one input of a multiplier 7 through a low pass filter (LPF) 3, while the Q phase component is applied to one input of a multiplier 8 through an LPF 4.
A carrier signal cos .omega..sub.c .multidot.t is applied from a signal source 5 to the other input of multiplier 7, which provides an I phase component cos .PHI.(t).multidot.cos .omega..sub.c .multidot.t of a modulated signal. A signal -sin .omega..sub.c .multidot.t, obtained by shifting the phase of the carrier signal from signal source 5 by .pi./2 by means of a phase shift circuit 6, is applied to the other input of multiplier 8, which itself provides a Q phase component -sin .PHI.(t).multidot.sin .omega..sub.c .multidot.t of the modulated signal. The resulting I phase and Q phase components can be represented in a one-to-one correspondence on the I and Q coordinates as shown in FIG. 2.
These I phase and Q phase components are added to each other by an adder 9 to become such a modulated signal as expressed by equation (1). The modulated signal is provided from an output terminal 10. Multipliers 7 and 8 and adder 9 form a quadrature modulating unit.
There is a case where an M-phase PSK (Phase Shift Keying) signal is generated by using such a quadrature modulator. FIG. 3 is a diagram conceptually showing the principle of generation of a .pi./4 shift QPSK (Quadri Phase Shift Keying) signal, which is one example of such an M-phase PSK signal.
Referring to FIG. 3, it is assumed that a signal point corresponding to I phase component and Q phase component data of a baseband signal at a certain time point exists at one of the points a, c, e and g on a unit circle having a radius of 1 as shown in FIG. 3. At a subsequent time point after a lapse of a predetermined time slot, the signal point shifts to one of the intersections b, d, f and h then situated between two virtual axes obtained by rotating the I axis and the Q axis by .pi./4 along the unit circle of a radius of 1. The I axis and the Q axis will be rotated by .pi./4 for each predetermined time slot in the same manner as described above, whereby the signal point sequentially shifts on the unit circle.
For example, if it is assumed that the signal point exists at the point a at a predetermined time point in FIG. 3 and the baseband signal does not change, the signal point shifts as a point.fwdarw.b point.fwdarw.c point.fwdarw.d point.fwdarw.e point.fwdarw.f point.fwdarw.g point.fwdarw.h point for every predetermined time slot, that is, at every .pi./4 rotation of the I axis and the Q axis. In this case, the I and Q phase data each takes the five types of values of "1", "1/.sqroot.2", "0", -1/.sqroot.2" and "-1" as can be seen from FIG. 3.
According to the digital cellular telecommunication system standard (RCR STD-27) of Japan and the cellular telecommunication standard (TIA-IS-54) of the North America, differential encoding is carried out in .pi./4 shift QPSK modulation. Because of such differential encoding, it is only necessary to consider a relative phase between continuous symbols. Therefore, by shifting the phase of the signal spatial diagram of FIG. 3 by .pi./8 as shown in FIG. 4, the I phase data and the Q phase data each has a level of a quadri value. Such .pi./4 shift DQPSK modulation by such differential encoding is generally referred to as ".pi./4 shift DQPSK modulation".
Description will now be given for a .pi./4 shift QPSK modulating system using such differential encoding. A digital baseband signal is serially applied to mapping circuit 2 (FIG. 1), with every two bits from the leading bit being converted (binary value/quarternary value converted) into parallel 2-bit symbol data (X.sub.k, Y.sub.k). FIG. 5 is a diagram schematically showing the manner of such binary value/quaternary value conversion.
Thus obtained 2-bit symbol data (X.sub.k, Y.sub.k) is further converted into a quadrature signal (I.sub.k, Q.sub.k) by differential encoding in mapping circuit 2. Conversion from the symbol data (X.sub.k, Y.sub.k) into the quadrature signal (I.sub.k, Q.sub.k) is carried out according to the following equation (2). EQU I.sub.k =I.sub.k-1 .multidot.cos{.DELTA..PHI.(X.sub.k, Y.sub.k)}-Q.sub.k-1 .multidot.sin{.DELTA..PHI.(X.sub.k, Y.sub.k)}Q.sub.k =I.sub.k-1 .multidot.sin{.DELTA..PHI.(X.sub.k, Y.sub.k)}+Q.sub.k-1 .multidot.cos{.DELTA..PHI.(X.sub.k, Y.sub.k) } (2)
In the above-described equation (2), .DELTA..PHI.(X.sub.k, Y.sub.k)=.DELTA..PHI..sub.k is defined based on differential coding rules shown in a table of FIG. 6. The quadrature signals I.sub.k, Q.sub.k thus obtained by mapping circuit 2 independently have their bandwidths limited by LPFs 3 and 4 (FIG. 1) and are thereafter applied to the quadrature modulating unit as the I phase component i(t) and the Q phase component q(t).
When T denotes a symbol period, and .PHI.(t)=.PHI..sub.k denotes a phase at t=kT, .PHI..sub.k is expressed as in the following. EQU .PHI..sub.k -tan.sup.-1 (Q.sub.k /I.sub.k) (3)
When a phase at an immediately preceding symbol, that is, at t=kT-T, is .PHI.(t)=.PHI..sub.k-1, .PHI..sub.k-1 is expressed as in the following. EQU .PHI..sub.k-1 =tan.sup.-1 (Q.sub.k-1 /I.sub.k-1) (4)
From the above-described equations (2), (3) and (4), the relation between .PHI..sub.k and .PHI..sub.k-1 can be defined as follows. ##EQU2##
From the above-described equation (5), the following relation can be obtained. EQU .DELTA..PHI. (X.sub.k, Y.sub.k)=.PHI..sub.k -.PHI..sub.k-1 ( 6)
Therefore, in order to demodulate the .pi./4 shift QPSK modulated signal, according to the above-described equation (6), at each maximum effect point, the phase .PHI.k at the symbol and the phase .PHI..sub.k-1 at an immediately preceding symbol are detected. Then, by subtracting the phase .PHI..sub.k-1 from the phase .PHI..sub.k, a phase change .DELTA..PHI.(X.sub.k, Y.sub.k) in one symbol section is found. Based on the table of FIG. 6, a corresponding X.sub.k, Y.sub.k can be obtained from the phase difference .DELTA..PHI.(X.sub.k, Y.sub.k). In a manner opposite to the manner shown in FIG. 5, serial data of . . . , a.sub.n-1, a.sub.n, a.sub.n+1, a.sub.n+2, . . . can be reproduced (demodulated) from X.sub.k, Y.sub.k. A digital demodulator for demodulating a digital phase modulated signal is disclosed in, for example, Japanese Patent Laying-Open No. 3-188737. FIG. 7 is a block diagram schematically showing a configuration of such a conventional digital demodulator.
Referring to FIG. 7, the digital demodulator includes an input terminal 101 to which a received digital phase modulated signal is applied, an input terminal 102 to which a symbol clock signal is applied, a limiter 103 generating a constant amplitude version of the digital phase modulated signal applied to input terminal 101, a synchronizing circuit 104 for sampling the symbol clock signal in response to an output signal of limiter 103, an oscillator 105 which generates a frequency at an integer multiple of a frequency of a carrier signal, a counter 106 for performing a counting operation in response to an output of oscillator 105, a latch circuit 107 for latching an output of counter 106 in response to an output of synchronizing circuit 104, a delay circuit 108 for delaying an output of latch circuit 107 for one symbol period (also referred to hereinafter as "section") in response to the output of synchronizing circuit 104, a comparison arithmetic circuit 109 for comparing the output of latch circuit 107 with an output of delay circuit 108 and thereby detecting a phase change in one symbol period so as to reproduce data therefrom, and a data output terminal 110 for providing data reproduced by comparison arithmetic circuit 109.
Operation of the digital demodulator shown in FIG. 7 will now be described. The amplitude of the digital phase modulated signal applied to input terminal 101 is limited by limiter 103 into rectangular wave signal with appropriate logic levels. On the other hand, the symbol clock signal which is a rectangular wave signal defined so that the times of its rising edges corresponds to times at which data is to be sampled, that is, the maximum effect point. The symbol clock signal is supplied to input terminal 102 from a symbol clock signal source, not shown. Synchronizing circuit 104 samples the symbol clock signal applied through input terminal 102 in response to each rising edge of the output signal produced by limiter 103. Therefore, a rising edge of the sampled symbol clock signal, that is, the output signal of synchronizing circuit 104, matches a zero-crossing point of the applied digital phase modulated signal.
On the other hand, oscillator 105 is structured so as to supply a clock signal of a frequency that is n times (where n is a positive integer) a frequency of the input digital phase modulated signal. Counter 106 1/n frequency-divides the clock signal to provide a count value of n division of a phase of one period of a carrier. The count value of counter 106 is held by latch circuit 107 at an occurrence of each rising edge of the output of synchronizing circuit 104 to be phase-quantized. The held count value represents the phase .PHI..sub.k of the digital phase modulated signal of the above-described equation (3).
The output of latch circuit 107 is applied to delay circuit 108 to be held therein until the next occurrence of a rising edge produced at the output of synchronizing circuit 104. The delayed value represents the phase .PHI..sub.k-1 at an immediately preceding symbol of the digital phase modulated signal of the above-described equation (4).
The output .PHI..sub.k of latch circuit 107 and the output .PHI..sub.k-1 of delay circuit 108 are applied to comparison arithmetic circuit 109. Comparison arithmetic circuit 109 detects the change .DELTA..PHI.(X.sub.k, Y.sub.k) of the phase in one symbol section. Comparison arithmetic circuit 109 further reproduces the 2-bit symbol data X.sub.k, Y.sub.k from the phase change .DELTA..PHI..sub.k based on the differential coding rules shown in the table of FIG. 6 to convert the same into serial data, and supplies the resulting serial data as demodulated data. The demodulated data is supplied through output terminal 110.
As described above, since an oscillation frequency of oscillator 105 is set to n times that of a carrier frequency of the digital phase modulated signal, phase quantization is carried out such that a resolution of a phase becomes 2.pi./n in demodulating. Therefore, if n is set to be sufficiently large, it is possible to obtain a sufficiently small resolution in phase.
As long as the oscillation frequency of oscillator 105 is accurately set to an integer n multiple of the carrier frequency of the digital phase modulated signal as described above, it is possible to obtain accurate phase change data .DELTA..PHI..sub.k. In the conventional digital demodulator as shown in FIG. 7, it is required to generate a symbol clock signal and to supply input terminal 102 with the same, separately from the input digital phase modulated signal. In the case of the above-described .pi./4 shift QPSK modulated signal, since an envelope of the modulated signal includes a frequency component of the symbol clock signal, a complicated analog circuit for extracting the frequency component is required in order to obtain the symbol clock signal. Therefore, it was impossible to constitute the entire conventional digital demodulator completely with digital circuits, thereby rendering a task of making a digital demodulator that is small in size and light in weight, through LSI implementation difficult.
Furthermore, in a mobile communication system such as a land mobile radio telephone and a portable radio telephone, individual oscillators are used on the transmitting side and the receiving side. Therefore, it is practically impossible to accurately set an oscillation frequency of oscillator 105 of a digital demodulator on the receiving side to exactly n times a carrier frequency of a digital phase modulated signal received from the transmitting side. When there exists a frequency offset between the carrier frequency on the transmitting side and the oscillation frequency of the receiving side as described above, a phase error component corresponding to the amount of the frequency offset is generated in the phase change data .DELTA..PHI..sub.k evaluated by comparison arithmetic circuit 109, which hampers accurate demodulation. Furthermore, such a phase error component is caused not only by the frequency offset between the transmitting side and the receiving side as described above, but also by a shift of the carrier frequency caused by Doppler phasing in mobile communication.
In the above-described conventional digital demodulator, there is a case where counter 106 is in an unstable state at an occurrence of a rising edge of the output signal produced by synchronizing circuit 104. If latch circuit 107 carries out latch operation in response to the output of synchronizing circuit 104 in such a state, it is not possible to carry out accurate phase quantization, which in turn makes it impossible to obtain accurate demodulated data.
In addition, in the conventional digital demodulator, in order to obtain a necessary small resolution in phase as described above, the oscillation frequency of oscillator 105 must be set to be sufficiently high (that is, n must be set to be sufficiently large) compared to the carrier frequency of the digital phase modulated signal. In general, in a CMOS digital circuit, it is known that the higher the frequency of an operating clock, the larger the power consumption. Therefore, in the conventional digital demodulator, when the frequency of the operating clock is increased in order to enhance phase resolution, power consumption increases. Especially in a communication terminal such as a battery-driven portable radio telephone, such increased power consumption causes various problems such as a shortened waiting time.